Expander development continues to advance with steady optimization efforts. Here’s this week’s update from the engineering team on FPGA acceleration for Expander.
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GF2-128 Hardware Performance: Completed the hardened hardware implementation of the GF2-128 arithmetic pipeline, achieving stable operation at 277 MHz on FPGA.
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End-to-End Proof Throughput: Achieved 75,000–77,000 proofs per second for the Keccak-based circuit in end-to-end FPGA testing, demonstrating substantial gains in overall proof generation throughput.
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NoC Performance Limitation: Current system performance is constrained by the on-chip Network-on-Chip (NoC) bandwidth, which is limited to around 250 MHz.
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Ongoing Optimization: Began exploring the use of soft NoC resources to improve data movement efficiency and relax routing congestion, with the goal of enabling higher sustained frequencies for large-scale proof workloads.
Stay tuned for more updates.
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